1. Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a semiconductor device having a triple well structure.
2. Description of the Related Art
With a semiconductor device in which a MOS transistor is used, variation due to noise in GND potential applied to a substrate causes variation in the back bias potential of a well region where the MOS transistor is formed. Accordingly, the threshold of the MOS transistor varies. As a result, the full performance of the semiconductor device cannot be obtained.
For example, a structure (triple well structure) where a p-type well region which is formed in a p-type semiconductor substrate and on which an n-type MOS transistor is formed is surrounded with an n-type well region is proposed as a method for reducing noise (see, for example, Japanese Patent Laid-Open Publication No. Hei3-030468). By adopting this method, noise from the semiconductor substrate can be cut off by a pn junction interface formed in the semiconductor substrate.
With a semiconductor device having a triple well structure, a structure in which a contact region for applying back bias voltage to a p-type well region is formed outside the p-type well region and an n-type well region is proposed to raise an integration level (see, for example, Japanese Patent Laid-Open Publication No. Hei10-199993). With this structure, the formation of hole-like conductive regions in the n-type well region is proposed to secure continuity between the p-type well region and the contact region.
FIG. 10A is a schematic sectional view showing an important part of an example of a semiconductor device having a triple well structure. FIG. 10B is a schematic plan view showing the inside of the example of a semiconductor device having a triple well structure. The schematic sectional view shown in FIG. 10A is taken along the line B-B of FIG. 10B and the schematic plan view shown in FIG. 10B is a sectional view taken along the line A-A of FIG. 10A.
As shown in FIG. 10A, a p-type well region 2 is formed in a p-type silicon (Si) substrate 4. An n-type well region 6 is formed beneath the p-type well region 2 so that it surrounds the p-type well region 2. n-type MOS transistors 1 are formed on the p-type well region 2. As shown in FIG. 10B, hole-like conductive regions 3 are formed in the n-type well region 6.
With the above structure, the p-type well region 2 which is shown in FIG. 10A and on which the n-type MOS transistors 1 are formed is electrically connected to the p-type Si substrate 4 through the hole-like conductive regions 3 shown in FIG. 10B. Accordingly, by applying VBB (back bias voltage) from a contact region 5, the back bias potential of the p-type well region 2 on which the n-type MOS transistors 1 are formed can be controlled. Furthermore, the p-type well region 2 on which the n-type MOS transistors 1 are formed is surrounded with the n-type well region 6, so noise from the p-type Si substrate 4 can be cut off.
With the semiconductor device having the triple well structure as shown in FIGS. 10A and 10B, however, the conductive regions 3 are unevenly distributed in the n-type well region 6. That is to say, the conductive regions 3 are formed in outer portions of the n-type well region 6 to avoid the influence of the injection of minority carriers from the p-type Si substrate 4 into the n-type MOS transistors 1.
As a result, paths from the contact region 5, via the substrate 4, through the conductive regions 3 to the n-type MOS transistors 1 may differ in length, depending on the positions of the n-type MOS transistors 1. For example, a path from the contact region 5, through a conductive region 3a shown in FIG. 10A, to an n-type MOS transistor 1a differs in length from a path from the contact region 5 through a conductive region 3b to an n-type MOS transistor 1b. As a result, the parasitic resistance of the path from the contact region 5 through the conductive region 3b to the n-type MOS transistor 1b is higher than that of the path from the contact region 5 through the conductive region 3a to the n-type MOS transistor 1a. 
If such a path the parasitic resistance of which is high exists in the substrate, the back bias potential of the p-type well region 2 cannot uniformly be controlled throughout by supplying back bias from the contact region 5 to the p-type well region 2 on which the n-type MOS transistors 1 are formed. As a result, the n-type MOS transistors 1a, 1b, and 1c cannot be controlled uniformly in a circuit which is made to operate with back bias potential varied. Furthermore, the influence of noise from the p-type Si substrate 4 or noise produced in the p-type well region 2 cannot be reduced significantly.